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On 9/29/2023 6:53 PM, MitchAlsup wrote:
> On Friday, September 29, 2023 at 1:03:02 PM UTC-5, Timothy McCaffrey wrote:
>> On Friday, September 29, 2023 at 1:07:47 PM UTC-4, BGB wrote:
>>
>>> I had considered possibly redesigning the pipeline at one point to allow
>>> a different mechanism for handling L1 misses. Namely marking registers
>>> for missed loads as "not ready" and then stalling the Fetch/Decode
>>> stages if the bundle would depend on a not-ready register (injecting the
>>> fetched data back into the pipeline once the load completes).
>>>
>> I think you just re-invented the CDC 6600 register scoreboard.
>> - Tim
> <
> Not quite:: CDC 6600 scoreboard scheduled the beginning of instruction
> execution and also the end of instruction execution {{in contrast Thomasulo
> only schedules the beginning of instruction execution}}
> <
> There are "all sorts of" mechanisms that provide RAW interlocking.
As-is, it is a blob of logic something like (psuedocode):
needStallRs =
((id2IdRs == exA1IdRn) && exA1Held) ||
((id2IdRs == exB1IdRn) && exB1Held) ||
((id2IdRs == exC1IdRn) && exC1Held) ||
((id2IdRs == exA2IdRn) && exA2Held) ||
((id2IdRs == exB2IdRn) && exB2Held) ||
((id2IdRs == exC2IdRn) && exC2Held) ||
((id2IdRs == exA3IdRn) && exA3Held) ||
((id2IdRs == exB3IdRn) && exB3Held) ||
((id2IdRs == exC3IdRn) && exC3Held) ;
needStallRt =
((id2IdRt == exA1IdRn) && exA1Held) ||
...
...
if(id2IdRs == REG_ID_ZZR)
needStallRs = 0;
if(id2IdRt == REG_ID_ZZR)
needStallRt = 0;
...
needStallInterlock = needStallRs || needStallRt || ...
Where the interlock stall mechanism causes the PF/IF/ID1/ID2 stages to
stall, with NOPs being forwarded into EX1.
The ready bit would likely be handled by internally expanding the
register fields, and then using one of the bits to signal whether or not
the value is ready to be used or is still waiting for an associated
operation to finish.
But, with ready flagging (and a mechanism to inject the values later),
it could be possible in theory to eliminate the need to stall the EX
stages (and possibly a way to "hide" some of the L1 misses).
...
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