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@REPLYADDR MitchAlsup <MitchAlsup@aol.com>
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On Saturday, September 30, 2023 at 2:34:08 AM UTC-5, Anton Ertl wrote:
> MitchAlsup <
Mitch...@aol.com> writes:
> >And in comparison:: I got almost all of that capability with 2 instructions
> >that guarantees forward and backwards compatibility, and scales with
> >machine resources.
> ><
> >2 versus 1300 :: Which one is really RISC ??
> There has been the argument that RISC is not about reduced numbers of
> instructions, but about reduced complexity. The Cartesian product
> does not make the instructions more complex, only more.
>
> The complexity of your two additional instructions is, from an
> architectural POV, the same as two nops, correct? That`s good!
<
Not quite NoOps:: the leading one provides a bit vector of registers that
are live-out from the loop; the trailing one does the ADD-CMP-BC part
of the loop.
>
> OTOH, it leads to the question why we need these instructions at all.
> Can you virtual vectors not be implemented as a pure
> microarchitectural mechanism without any additional instructions?
<
It might be possible to recognize a loop as something special that can
be performed with non-standard HW mechanisms--it is just easier when
the loop self-identifies.
<
> What do the additional instructions buy?
<
Sequencing semantics--mainly in what does NOT need to be performed
(the live-outs for example minimizes the work of exiting the loop).
>
> - anton
> --
> `Anyone trying for "industrial quality" ISA should avoid undefined behavior.`
> Mitch Alsup, <
c17fcd89-f024-40e7...@googlegroups.com>
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