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@REPLYADDR SpainHackForth <jemo07@gmail.com>
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@TZUTC: -0700
@PID: G2/1.0
@TID: FIDOGATE-5.12-ge4e8b94
John, after the hardship of going thought all the messages in this
thread, I`m really interested in seen you work.
I was truing to look at the OP and make some sense of it, here
is what I came up with for the following as an example:
1 1C >XBCS AD D - - H" DR_RRB_AC" ` EMU_DR_RRB_AC ` NOP SIMPLE-OP: DR_RRB_AC
1 1C: Parameter values of 1 1C can be understood as a single hex
value 0x1C representing some kind of opcode or identifier for the
operation.
>XBCS: This is likely a transformation or a command to convert the
previous value.
AD D - -: These could be flags or additional parameters for the
operation. They might indicate how the operation behaves, modifies data, or
interacts with other parts of the system.
H" DR_RRB_AC": Looks like it`s a label or identifier for the
operation. It`s named DR_RRB_AC and would be referenced elsewhere.
` EMU_DR_RRB_AC `: This is fetching the execution token (xt) of the
word EMU_DR_RRB_AC. Possible a word for a subroutine or handler that gets
called when the operation is executed.
NOP: No Opp.
SIMPLE-OP: DR_RRB_AC: This is the actual declaration of the
operation. It`s named DR_RRB_AC, and all the preceding parameters and values
describe its behavior and properties.
Code Type: The type or category of the instruction.
src: Source operand (e.g., a register or memory location).
dst: Destination operand.
Dsrc and Ddst: Possibly deferred or delayed source and destination operands.
instr string: A human-readable string representation of the instruction.
emulation operation: This likely refers to how the instruction should
be emulated. It could be used in a software emulator to mimic the
behavior of the real hardware.
Register: They look allot like RISC Arm, so I based my self on that.
Here is my attempt to put this into some sort of verilog format:
// Define the registers and flags
reg [15:0] Treg; // 16-bit T register
reg [15:0] accumulator; // 16-bit accumulator
reg [15:0] data_reg; // 16-bit data register
...
reg carry_flag; // Carry flag
reg flag; // General flag
...
// Define the operations
always @(posedge clk) begin
case (operation_type)
`>XBCS`: begin
// Implement the >XBCS operation
// Example: data_reg = Treg + accumulator + carry_flag;
...
end
`>CS`: begin
// Implementw the >CS operation
...
end
`>MA`: begin
// Memory Addressing: Load the accumulator with the value at the
memory address
accumulator = memory[address];
end
`AC>MA`: begin
// Memory Addressing: Store the accumulator value to the memory
address
memory[address] = accumulator;
end
...
`TR>DR`: begin
// Move data from T register to data register ( assuming that is
the meaning )
data_reg = Treg;
end
`AC>DR`: begin
// Move data from accumulator to data register
data_reg = accumulator;
end
`0>DR`: begin
// Set data register to 0
data_reg = 16`b0;
end
`AC_OR_TR>DR`: begin
// Logical OR between accumulator and T register, result to data
register ( just making this up )
data_reg = accumulator | Treg;
end
`IF_CRY+JMP`: begin
// Conditional jump based on carry flag ( If that is correct )
if (carry_flag) begin
program_counter = jump_address;
end
end
...
// All the Ops form the code.
endcase
end
// Emulation functions
function EMU_TR>DR;
begin
// Emulate the TR>DR operation what ever that is.
...
end
function EMU_AC>DR;
begin
// Emulate the AC>DR operation what ever that is.
...
end
...
--- G2/1.0
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