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@REPLYADDR Quadibloc <jsavard@ecn.ab.ca>
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On Saturday, September 30, 2023 at 2:40:16 AM UTC-6, Quadibloc wrote:
> On Monday, September 25, 2023 at 4:40:46 AM UTC-6, Quadibloc wrote:
> >
http://www.quadibloc.com/arch/per04.htm
> >
> Now, I have updated the material on this latter page, in order to
> reflect the fact that modern DRAM chips, in order to perform at
> maximum efficiency, need to be accessed in units of sixteen
> consecutive - and aligned - locations.
>
> So now, instead of a major sacrifice of memory bandwidth, we can
> use memory at full bandwidth, but for two of the possible memory
> widths to be supported, we need to leave a small fraction of memory
> unused - 1/64th for the 36-bit word, and 3/128ths for the 60-bit
> word.
>
And then I realized another update was needed.
The 48-bit word length is native to this design, so logical addresses
correspond to physical addresses - except for features like paging and
so on.
The 64-bit word length still just requires a divide-by-three circuit to
translate from logical to physical addresses.
But now, instead of just requiring multiplication, division is also required
for the logical-to-physical conversion for the 36-bit and 60-bit word lengths!
Divide-by-21 for 36 bits, and divide-by-25 for 60 bits. However, these are
still achievable simply, because three is 11 in binary, seven is 111 in binary,
and fifteen, a multiple of five, is 1111 in binary - so the end-around-carry
design for a simple and fast division circuit is applicable, even though in
both cases two have to be cascaded.
John Savard
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